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In this column we explain the COM Express specification in a series of tutorials. Last month we gave a high-level overview of the specification. This month we take a closer look at PCI Express link configurations, pin-outs and carrier board configuration EEPROM.
The PCI Express lanes can be configured in links of widths of 1, 2, 4, 8, 16 or 32 lanes. The COM Express standard does not restrict which link widths and in which order these links can be configured. A configuration EEPROM on the carrier board indicates to a module which link widths and in which order these links should be configured.
The only aspect of the configuration that is dictated by the specification is the order in which the lanes are being configured in a link. For this matter the maximum of 32 possible lanes is logically divided in 4 "buckets" of 8 lanes each. See Figure 1. Note how bucket 1 spans both row pairs AB and CD. This is due to the fact that pin-out type 1 has been defined with a maximum of 6 PCI Express lanes.
Figure 1. PCI Express lanes logically divided into buckets
The widest link(s) in a bucket is (are) first configured, starting in the lowest lane number in the bucket. Figure 2 illustrates this for link orderings in a single bucket (bucket n) for different combinations of link widths. The x16 and x32 links span 2 and 4 buckets, respectively. Figure 2 illustrates this for a x16 link, spanning bucket n and adjacent bucket n+1. It also illustrates a x32 link spanning all 4 buckets defined in the specification.
Figure 2. PCI Express link configurations in and across buckets
The COM Express specification includes 5 pin-out configurations as was explained in Part II of this series of articles. Each of these 5 pin-out types has minimum and maximum allowed ports defined for each functional interface. This is shown in Table 1.
| Type 1 Row AB (min/max) |
Type 2 IDE + PCI (min/max) |
Type 3 PCI (min/max) |
Type 4 IDE (min/max) |
Type 5 (min/max) |
|
|---|---|---|---|---|---|
| PCI Express Graphics1 | N/A | 0/1 | 0/1 | 0/1 | 0/1 |
| PCI Express bucket 1 | 2/6 | 2/6 | 2/6 | 2/8 | 2/8 |
| PCI Express bucket 2-4 | N/A | N/A | NA | 0/8 | 0/8 |
| SDVO2 | N/A | 0/2 | 0/2 | 0/2 | 0/2 |
| LVDS | 0/2 | 0/2 | 0/2 | 0/2 | 0/2 |
| VGA | 0/1 | 0/1 | 0/1 | 0/1 | 0/1 |
| TV-Out | 0/1 | 0/1 | 0/1 | 0/1 | 0/1 |
| IDE3 | 0/1 | 0/1 | 0/1 | 0/1 | 0/1 |
| SATA/SAS | 2/4 | 2/4 | 2/4 | 2/4 | 2/4 |
| AC '97 | 0/1 | 0/1 | 0/1 | 0/1 | 0/1 |
| USB 2.0 | 4/8 | 4/8 | 4/8 | 4/8 | 4/8 |
| LAN4 | 1/1 | 1/1 | 1/3 | 1/1 | 1/3 |
| PCI Bus5 | N/A | 1/1 | 1/1 | N/A | N/A |
| LPC Bus | 1/1 | 1/1 | 1/1 | 1/1 | 1/1 |
| Express Card | 1/2 | 1/2 | 1/2 | 1/2 | 1/2 |
| GPI | 4/4 | 4/4 | 4/4 | 4/4 | 4/4 |
| GPO | 4/4 | 4/4 | 4/4 | 4/4 | 4/4 |
| SMBus | 1/1 | 1/1 | 1/1 | 1/1 | 1/1 |
| I2C | 1/1 | 1/1 | 1/1 | 1/1 | 1/1 |
| Watch dog timer | 0/1 | 0/1 | 0/1 | 0/1 | 0/1 |
| PC speaker | 1/1 | 1/1 | 1/1 | 1/1 | 1/1 |
| External BIOS ROM | 0/1 | 0/1 | 0/1 | 0/1 | 0/1 |
| Resets | 1/1 | 1/1 | 1/1 | 1/1 | 1/1 |
| Thermal protection | 0/1 | 0/1 | 0/1 | 0/1 | 0/1 |
| Battery low | 0/1 | 0/1 | 0/1 | 0/1 | 0/1 |
| Suspend | 0/1 | 0/1 | 0/1 | 0/1 | 0/1 |
| Wake | 0/2 | 0/2 | 0/2 | 0/2 | 0/2 |
| Power button | 1/1 | 1/1 | 1/1 | 1/1 | 1/1 |
| Power good | 1/1 | 1/1 | 1/1 | 1/1 | 1/1 |
Table 1. Summary of capabilities defined for COM Express functional blocks
The COM Express specification dictates that functional interfaces for which a range of ports is defined, must be populated starting from the lowest port number. For instance, suppose a manufacturer designs a module with 6 USB 2.0 ports. These ports must start from port #0 and progress to port #5, without any gaps.
OEMs need to be aware of interface variability that can occur, according to Table 1, between modules of different manufacturers. Hence, a request for quote needs to be explicit in terms of the interface requirements, if incompatibility is to be prevented.
The variability in the number of ports for the different functional interfaces in Table 1 can cause problems when a module with less ports is inserted on a carrier board that operates a larger number of ports for this functional interface. For instance, a carrier board, which has been designed for pin-out Type 2 modules, has 3 Ethernet interfaces. A Type 2 module, which only supports one Ethernet interface, is inserted on the carrier board. If this situation is left undetected, two of the carrier board's Ethernet ports will be non-operational. As a consequence, critical failures may occur during operation, which are normally not detected at power up.
To detect such issues, the COM Express specification recommends implementation of a configuration ROM on carrier boards. This allows a module to query the configuration ROM via it's I2C interface, to determine if it has a mismatch with the number and type of functional interfaces used on the carrier board and to correctly configure its ports or generate error messages. Error message formats are module manufacturer dependent and are not defined by the COM Express specification.
Table 2 explains which functional interfaces the configuration ROM describes.
| Functional Interface | Explanation |
|---|---|
| PCI Express | Description of width of each link and starting lane number for each link used. |
| SATA/SAS | Description of which port types (SAS or SATA) and which port numbers are used. |
| LAN | Description of which Ethernet ports are implemented. |
| USB | Description of the number of USB ports used. |
| ExpressCard | Description of which ExpressCard PCI Express and USB ports are implemented and to which PCI Express lanes and USB ports these are mapped. |
| TV-Out | Description of which type of TV-Out interface is used (component, composite or S-Video). |
| VGA | Description whether or not the VGA is used. |
| LVDS | Description of which LVDS channels are used. |
| SDVO | Description of which SDVO channels are used. |
| AC'97 | Description whether or not the AC'97 link is used. |
| Watchdog timer | Description whether or not the watchdog timer is used. |
| External BIOS ROM | Description whether or not the external BIOS ROM bypass signal is used. |
| Thermal protection | Description whether or not the thermal protection signal is used. |
| Battery low | Description whether or not the battery-low alarm signal is used. |
| Suspend | Description whether or not the suspend signals are used. |
| Wake | Description of which wake signals are used. |
Table 2. Summary of functional interfaces covered by the configuration ROM
End of Part III
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