Kishan Jainandunsing
(February 2006)

Embedded World, February 2006, Nurnberg, Germany – Intel announced its Core Duo dual-core CPUs for the embedded market space. These CPUs are based on the company’s new Yonah architecture in a 65nm process with improved power efficiency over the earlier Dothan and Banias architectures and are available in 1.66GHz and 2.0GHz speed grades. With Core Duo the company is breaking away from the Pentium M branding it used for the Dothan and Banias architectures, putting emphasis on the multi-core aspects of the new CPUs.

The Core Duo has a 667MHz system bus and 2MB of level-2 cache. Just as the Pentium M processors, the Core Duo processors use Enhanced Intel SpeedStep Technology with dynamic core voltage and frequency switching for more efficient power/performance ratios. New on the Core Duo is core-independent speed stepping. Also new on these processors is the ability to dynamically size the shared L2 cache between the two cores and by sharing the L2 cache, the cores can write data into each other’s L2 cache domains, without the need for a roundtrip between the L2 cache and system memory.

The cores can also go independently and dynamically into power savings sleep modes, reducing power when the application load can be handled sufficiently by a single core. The Core Duo processors can share an application’s load across the two cores and can run multiple operating systems simultaneously.

So far the company has not made any announcements around a product line of entry-level Core Duo processors with smaller L2 caches, as it did under the Celeron M branding for CPUs with half the L2 cache size of the Pentium M processors. The company has also not announced plans to offer its Core Solo, single-core Yonah architecture, processors for embedded applications. The 1.66GHz and 2.0GHz Core Duo CPUs are priced at $316 and $423 in quantities of 1,000 units, respectively. Read more in the company’s press release.